1. Field of the invention
The present invention relates to a process for forming multilayer wiring patterns on a substrate. More particularly, a self-aligned process is taught for fabricating polyimide overlayers having both wiring and interconnection metallurgy. Each layer fabricated in this manner is unique both in its structure and its integrity.
2. Description of the Prior Art
Semiconductor packaging technology has progressed beyond the simple sintered inorganic dielectrics having co-fired metallurgy, due to the speed and dimensional requirements of advanced devices. The use of thin metallized layers of organic dielectrics has become widely accepted as the solution addressing the new technological requirements. Ideally, an underlying substrate of standard sintered inorganic material provides the interconnection capability for mating with the next level of packaging (e.g. pins), the basic power supply wiring, and a metallized top surface for supporting multiple organic signal wiring layers. Structures have been proposed having as many as five (5) thin organic layers with associated signal metallurgy on the top surface of a sintered inorganic substrate. However, the fabrication of multilayer metallized organic structures is difficult to achieve using the processing techniques which are standard in the semiconductor and package processing industries.
Metallization is challenging due to the limitations of the lift-off techniques. In lift-off, the substrate is coated with a polymeric, radiation-sensitive layer (resist layer) which is subsequently patterned in such a manner as to expose the underlying substrate in those areas in which it is desired to deposit metallurgy. The metallurgy is then deposited over the exposed substrate areas and resist pattern. "Lift-off" occurs when the patterned resist material is dissolved, or otherwise removed, taking with it the undesired metallurgy and leaving the desired metal pattern. Deposition of the desired dielectric about the remaining metal and planarization of same is then required. The drawbacks of this fabrication technique include the high possibility of removal of the desired metallurgy with the resist and undesired metallurgy, particularly when the linewidths of desired metallurgy are very small. In addition, the patterning requires precise alignment in order to achieve metal deposition on, and thereby electrical connection to, the appropriate underlying areas on the substrate.
The metal deposition and removal technique of chemical-mechanical (or chem-mech) polishing has adequately addressed the concern of unnecessarily removing desired metallurgy at the same time as potentially eliminating the step of depositing the desired dielectric about the formed metal pattern. In chem-mech polishing, the polymeric, radiation-sensitive resist layer can be left in place as the dielectric material, if indeed it can act as an adequate insulator for the purposes of the electronic device. However, the difficulty of proper alignment to contact the underlying substrate is not addressed by the chem-mech method. Alignment is not only a processing challenge, but also limits the final structures. The common solution to alignment concerns is to overcompensate by depositing increasingly larger features with each subsequent layer in order to assure capture of the underlying feature. The result is a limitation on the number of layers due to this feature "growth" and electrical shorting concerns.
Further challenges to fabrication of a multilayer organic structure include adhesion of the polymeric material to both the associated metallurgy and the subsequently-deposited layers of polymeric material. The adhesion, the mechanical integrity and the electrical integrity of an organic layer can be influenced by the amount and type of processing to which it is exposed. Therefore, it is additionally desirable to minimize the processing of the multilayers in order not to compromise the properties of the materials and thereby the mechanical and electrical integrity of the structure.
In the past, the steps required for fabricating a level of organic packaging, as is herein defined as the wiring layer plus a via/interconnection layer, comprised the following steps:
(a) deposition of first organic resist layer; PA1 (b) patterning the first organic resist layer through a fine featured mask (may include additional removal step depending upon patterning technique); PA1 (c) deposition of wiring metallurgy on and about first patterned resist layer; PA1 (d) removal of resist layer and excess overlying metal, leaving desired metal pattern; PA1 (e) deposition of first insulative material on and about desired wiring metal pattern; PA1 (f) removal of excess first insulative material on wiring metal; PA1 (g) deposition of second organic resist layer; PA1 (h) patterning of second resist layer through another fine featured mask (again, may require additional removal step); PA1 (i) deposition of via metallurgy on and about second patterned resist layer; PA1 (j) removal of second resist layer and overlying via metallurgy; PA1 (k) deposition of second insulative material on and about via metallurgy; and PA1 (l) removal of excess second insulative material from surface of via metallurgy. PA1 (a) deposition of first patternable insulation layer; PA1 (b) patterning first insulation layer through fine feature mask (may include both patterning and removal steps); PA1 (c) deposition of wiring metallurgy on and about first insulation layer; PA1 (d) removal of excess metallurgy deposited on surface of first insulation layer by chem-mech polishing; PA1 (e) deposition of second patternable insulation layer; PA1 (f) patterning second insulation layer through fine featured mask (again, may include patterning and removal steps); PA1 (g) deposition of via metallurgy on and about second patterned insulation layer; and PA1 (h) removal of excess via metallurgy from the surface of the second insulation layer by chem-mech polishing.
The invention of chem-mech polishing, as referred to above and as is taught in Chow et al. U.S. Pat. No. 4,702,792, eliminates several steps of the process which is then consolidated into the following:
The processing still requires detailed masks at each patterning step and two rigorous polishing steps. There is a need to further simplify the fabrication method to insure both ease and integrity of the resulting structure.
It is therefore an objective of the present invention to provide a method for fabricating multilayer metallized organic layers and to provide a resulting structure having good mechanical and electrical integrity.
It is a further objective of the subject invention to reduce the processing requirements for fabrication of a multilayer metallized organic structure.
It is yet another objective of the present invention to provide a "self-aligned" method for fabricating multilayer metal and organic structures to reduce alignment concerns therein.
It is another objective of the present invention to avoid the "growth" of features due to alignment concerns.